RISC-V Linker Script Notes

This memory map defines various memory regions and their attributes. Each region's origin address and length are specified. The map includes data memory, instruction memory, cacheable and non-cacheable sections, and regions specifically used for bootloading, initialization, and system startup.

1. envm (rx)

   • Origin: 0x20220100
   • Length: 128k - 0x100
   • This section holds the reset vector, starting from page 1 of the envm region. It is read-only (rx) for security and stability.

2. dtim (rwx)

   • Origin: 0x01000000
   • Length: 7k
   • DTIM (Data Tightly Coupled Memory), used for rapid memory access by the processor, is read-write-execute (rwx).

3. e51_itim (rwx)

   • Origin: 0x01800000
   • Length: 28k
   • Instruction memory for the E51 processor. It's read-write-execute (rwx) for instructions and data.

4. u54_x_itim (rwx) (for U54 cores 1 to 4)

   • Origin: 0x01808000 (U54_1)
   • Length: 28k
   • The other U54 cores (2, 3, 4) have similar memory maps for their instruction regions.
   • Each U54 core has a dedicated 28k memory region to execute its own instructions.

5. l2lim (rwx)

   • Origin: 0x08000000
   • Length: 256k
   • L2 Cache Limit region, used for low-latency, fast data access for the CPU cores.

6. scratchpad (rwx)

   • Origin: 0x0A000000
   • Length: 256k
   • General-purpose scratchpad memory for storing temporary data during operations.

7. switch_code_dtim (rx)

   • Origin: 0x01001c00
   • Length: 1k
   • Used during the switching of the envm clock for executing necessary code when transitioning.

These sections define memory regions for accessing DDR RAM, with varying cache configurations and sizes:

• ddr_cached_32bit (rwx)

  • Origin: 0x80000000
  • Length: 768M
  • 32-bit cached DDR memory for general-purpose use.

• ddr_non_cached_32bit (rwx)

  • Origin: 0xC0000000
  • Length: 256M
  • 32-bit non-cached DDR memory, slower but often used for peripherals or large buffer storage.

• ddr_wcb_32bit (rwx)

  • Origin: 0xD0000000
  • Length: 256M
  • WCB (Write-Combining Buffer) used to optimize write operations.

• ddr_cached_38bit (rwx)

  • Origin: 0x1000000000
  • Length: 1024M
  • 38-bit cached DDR memory, a larger address space for high-performance applications.

• ddr_non_cached_38bit (rwx)

  • Origin: 0x1400000000
  • Length: 0k
  • Reserved space, not currently in use.

• ddr_wcb_38bit (rwx)

  • Origin: 0x1800000000
  • Length: 0k
  • Reserved space for 38-bit WCB operations.

• UNITITALISED_MEM

  • Size: 16B
  • A small amount of uninitialized memory, used to store information retrieved from the bootloader on start-up.

• HEAP_SIZE

  • Size: 0k
  • Needs to be calculated based on the application requirements for dynamic memory allocation.

• STACK_SIZE_U54_APPLICATION

  • Size: 8k
  • Stack size allocated for the U54 application (single hart).

• SECTION_START_ADDRESS

  • Address: 0x80000000
  • This is the reset address for the system, typically where the processor starts execution after power-up or reset.

• The memory sections are carefully mapped with specific regions for various tasks, such as booting (envm), execution (U54 cores), and data manipulation (DTIM, scratchpad, DDR).
• Cacheable and non-cacheable memory regions allow optimizing performance for certain types of data, such as frequently accessed variables or large, slow buffers.
• Memory sizes are specific and should be adjusted based on the application’s needs, particularly the heap and stack sizes.